As used herein, the term "semiconductor device" refers to a silicon chip or die containing circuitry, and the term "semiconductor device assembly" refers to the semiconductor chip and associated packaging containing the chip, including leads such as for connecting to a socket or a circuit board, and internal connections, such as bond wires, of the chip to the leads.
Commonly-owned U.S. Pat. No. 4,800,419, entitled SUPPORT ASSEMBLY FOR INTEGRATED CIRCUITS and filed on Jan. 28, 1987, discloses a composite support assembly for an integrated circuit chip. The support assembly includes a rigid lead frame that is attached to a relatively thin, flexible, tape-like structure. The tape-like structure includes a metallic layer that is etched with inner and outer lead "fingers" allowing for a short pitch, high density arrangement of the lead fingers, thereby enabling bond wires that connect a semiconductor chip to the support assembly to be relatively short. The metallic layer is supported by a segmented plastic film layer, preferably formed of KAPTON (trademark of DuPont Corp.).
Commonly-owned U.S. Pat. No. 4,771,330, entitled WIRE BONDS AND ELECTRICAL CONTACTS OF AN INTEGRATED CIRCUIT DEVICE and filed on May 13, 1987, discloses an integrated circuit device package including a rigid frame and flexible tape assembly having wire leads between the die attach pad, conductive lead fingers and the integrated circuit (IC) chip. A dam structure prevents resin flow to ensure proper wire bonding.
Commonly-owned, copending U.S. patent application No. 115,228, entitled METHOD AND MEANS OF FABRICATING A SEMICONDUCTOR DEVICE PACKAGE and filed on Oct. 30, 1987, incorporated by reference herein, discloses a semiconductor device assembly having a patterned conductive layer, including a die attach pad and a plurality of leads, and a patterned insulating layer. A semiconductor die is seated on the die attach pad and is connected, such as by bond wires, to the leads. A silicone gel, such as Dow Corning Q1-4939, having a 1 to 10 mixing ratio of curing agent to base, is applied over the bond wires. A body frame, preferably made of a polymer material such as RYTON (trademark of Phillips Chemical Co.) is positioned around the die, and an encapsulant material, such as HYSOL CNB 405-12 (trademark of Hysol) is distributed within the RYTON frame over the semiconductor die and die connections.
Commonly-owned, copending U.S. patent application Ser. No. 380,174, entitled STRIP CARRIER FOR INTEGRATED CIRCUITS and filed on Jul. 14, 1989, incorporated by reference herein, discloses a semiconductor device assembly having a patterned conductive layer and a patterned insulating layer, and mounted to a strip carrier (surrogate lead frame) providing mechanical rigidity to the semiconductor device assembly during assembly thereof. After assembly, the packaged semiconductor device assembly is excised from the strip carrier.
The aforementioned patents and applications relate to semiconductor device assemblies having a high (and dense) lead count and that may operate at high speeds. Such high speed semiconductor devices must generally be provided with capacitance across the power leads to ensure noiseless direct current (DC), even when the best of power supplies are provided, since noise can easily be induced onto the power leads by adjacent signal leads. In this regard, the ultimate solution would be to have capacitors (for power lead filtering) located directly on the semiconductor device (chip). Unfortunately, such a solution is not feasable. Therefore, it becomes highly desirable to locate the capacitors as close to the semiconductor device as possible. In this regard, packaging considerations become paramount. Therefore, it has been generally accepted to mount the capacitors external to the semiconductor device assembly, such as within or adjacent a socket into which the semiconductor device assembly is mounted. In real world terms, this means that the capacitors may be located on the order of a half inch or more away from the semiconductor device. Such a "remote", external mounting of the capacitor(s) presents a real limitation to the operating speed of the semiconductor device. Simply put, capacitors located outside the package of the semiconductor device assembly do not help with problems occuring within the package. These problems include stray inductances, ground plane bounce and voltage surges.
In the prior art it has been known to incorporate a relatively large capacitor within in the semiconductor device assembly as part of the die attach pad. However, this solution has a major drawback in that the thermal expansion characteristics of the capacitor are not readily matched to the thermal expansion characteristics of the remaining components of the semiconductor device assembly. Alternatively, it has been known to incorporate a relatively large capacitor on top of the entire semiconductor device assembly. This solution suffers from a tendency to catch on neighboring objects. Neither of these solutions properly solves the problem of getting a capacitor very near to the semiconductor device.